Your 1st Silicon Emergency Service

For FABLESS design houses we offer FIB CIRCUIT EDIT services for rapid verification and electrical debug of 1st Silicon.

FIB Circuit Edit Service for Chip Designers and Layout Engineers

FIB circuit edit – for when your 1st Silicon needs a mask change before volume production.

When “1st time right” is not right, choosing the best partner for FIB IC Nano-Surgery is a critical decision for a design manager. It is important to know who you can trust to quickly help you mitigate the serious technical and commercial disruption to your NPI process, and the pitfalls to avoid.

You need to know –

Can I have working devices in a few hours or days? – NanoScope specialises in the fastest turnaround times in the Europe and Middle East time zones.

What’s my Yield going to be? – Our world-beating better than 95% 1st time success rate has been standard since we opened in 2006, and we’ve been doing this longer than anybody – since 1992. For the most complex fixes we offer yield predictions BEFORE you commit, based on 28+ years of experience.

How can I reduce the risks? – NanoScope offers free consultation on all projects, we work directly with your designers to maximise the fix yield, and reduce the time needed for any fix BEFORE we quote.

What if the intervention doesn’t fix the problem? – 30% of all fixes specified by designers do not fix the correct electrical problem found. BUT a wrong fix correctly implemented proves that a different metal fix is required – this saves an entire metal fix FAB run, and helps you understand the REAL problem more quickly.

I’ve had bad results/low yield before, why are you different? – We are FIB technologists and we specialise in Semiconductor device Nano-Surgery. These are specific skills required for delivering the best advice and the highest yields. Respect the complexity of the process, and choose your partner based on what they need to know.

Are you value for money? – Do you choose a FIB partner based on their hourly rate? Or for convenience? (using the FA lab at your Test house or Reliability partner). Maybe you use a University with a new FIB-SEM? (the wrong tool). If the operator was trained by a vendor (limited knowledge), or mostly does Failure Analysis (the wrong application), or research (unrelated), or they are just cheap (why?), what value can they add in reality?

Getting you the right fix for the right problem in the shortest time is how we add value to your business.

FIB Circuit Edit Process Map

FIB Circuit Edit: Full process flow

First – Check the structure

Sometimes information is limited, but the device construction defines how we can modify it. We use non-destructive X-ray and/or CSAM to understand the lead frame design, die attach/stacking/size/position/orientation, bondwire type and layout etc. to optimise your opening strategy.

Second – Open the device – economically, while leaving it fully functional

The die surface must be open at the point of intervention(s), giving sufficient access, a clean surface, and without compromising how the device will be tested AFTER the intervention is complete. These steps are defined by 4 things

  1. Structure and materials – There are different approaches for Ceramic, Metal, Hybrid, Plastic, Eco Plastic, Chip and Wire, Globtop, Embedded etc. The Bond wires (and other metal structures) can be sensitive to acid and sometimes a laser pre-cavitation step first. Ceramics and Metal cans need mechanical processing.  Conformal coatings and solder masks, glob topping and other protections all have different requirements.
  2. Intervention requirements – How much access do we need? are the new FIB tracks long (mm’s) or local (μm’s). Does the fix require maximum gas flux? Closer nozzle approach needs more room. If multiple sites need modification then a full decap may be the best approach.
  3. Post fix testing requirements – how will the device be tested AFTER nano-surgery. If you’re using a socket, then preserving the lid for clamping is essential for easy testing. If you’re re-flowing the chip, it may need resealing to protect the fix. WLCSP has different issues again.
  4. Re-sealing – refilling an opening is sometimes required, and materials vary in quality, reactivity, cost and curing time.

Third – Optimise the Fix for best results

Chip designers are not FIB technologists and they don’t construct chips. The limitations and capabilities of FIB plus the nano-surgery process and how to optimise it, plus knowing the structure and behaviour of the materials to be modified, are all required for a successful fix. The final version after the FIB circuit edit should yield well, and be economic to implement.

By working with your designers we can advise how to achieve this result. Changing the location, target layers and routes of the FIB operations by just a few microns, can change an intervention yield by 100% and the costs too.

Fourth – Implement the Fix

Processing the devices with the correct ESD handling protocols, mounting , grounding, FIB work, cleaning, inspection (pre- and post), shipping and support in the shortest time frame.

The fix must also survive the testing process. If the device is to be heated – then standard Platinum depositions will not survive (it’s only 14% Pt and 86% Hydrocarbon), and solder can short out FIB fixes if not properly protected.

Fifth – Results review and remedial actions

Confirming intervention success and quickly completing remedial actions or rework are as important as delivering devices on time. If alternative fixes are necessary, these are often needed more rapidly than before. This are all part of a successful process and how NanoScope’s FIB circuit edit service ensures you have working devices in a few hours or days, with our >95% success rate.

Multi Layer Fix in FIB Circuit EditFlow chart of FIB Circuit Edit in the R&D processContacts through 2 higher metal layers via FIB circuit EditNano-Surgery Design FIB circuit EditTilted view of 2 tracks, cuts and cleanup during FIB circuit editGDSII overlay during FIB circuit editLong Fix during FIB circuit edit

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If you are interested in working together, send us an inquiry and we will get back to you straight away.

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European / Middle East Issue: Winter 2022

European / Middle East Issue: Winter 2022 A new IC design FIB Nano-surgery datapoint, our JEDEC MSL Rel-test services and Euros discount. Dear NanoScope Customer, greetings in our first email since COVID. For Silicon DESIGNERS we’ve got a new node success data point, for RELIABILITY Engineers there are new MSL testing services, for EU customers there is our 1€ = 1£ deal, plus NanoScope is growing. First FIB circuit nano-surgery fix to a 7nm node, from the FRONTSIDE.  Our unique expertise has allowed us to successfully modify this advanced 7nm process with 13 metal layers at the M2 level, from the front. The device die was then flipchip packaged and tested with a 65% yield. The benefit for the customer concerned was ‘invaluable’.  Watch out for the upcoming article on this story. Don’t forget to read our 1st article on ‘How to get the most benefit from IC Nano-Surgery” – part 2 coming soon. Launching our low cost MSL testing service for packaged parts for both R&D and production Reliability. All MSL testing is done to JEDEC standards, but now for the first time customers can choose to have a JEDEC CERTIFIED or an UNCERTIFIED test. R&D lots don’t require certification, so why not save 30% on your MSL trials of new packages? Loading a test lot for Temperature Humidity Bias testing (THB) New colleague – supporting accounts, logistics, orders, quality and billing We’re pleased to introduce Janine Stone, who is now managing project administration and compliance at NanoScope, adding much needed bandwidth for our technical offerings. Contact Janine here. Please welcome Janine Stone to the NanoScope team. We’re re-introducing our 1€ = 1£ exchange rate. To help our EU customers during this period of economic chaos, our 1:1 exchange rate adds clarity, security and a 16%... read more

How to get the most benefit from FIB IC Nano-surgery?

There are many advantages of correcting an IC design with FIB Nano-Surgery, but sometimes there are also problems, and many designers have been put off the technique. Did your last FIB work as you expected? Or was the yield low? or you got results you couldn’t explain? A quick recap of the reasons to do a FIB edit and how you would go about it, might be helpful. SCENE: So you’ve taped out your big new design, and 4 months and ₤400,000 /$/€ later, your 1st Silicon devices have arrived for tests to start. And immediately, there’s a problem. If you are lucky, then a normal functional test has failed and after a few days of head scratching it becomes clear what the cause is, and what the most likely metal fix should be. If you are unlucky and it’s more subtle, but still a show stopper for customer acceptance, then the fix strategy may be less obvious. Either way, prompt action is required and there are some difficult decisions to make. Your colleagues, customers and suppliers are all waiting to help get your product to market. Then there is the expense and the delays: to testing, to qualification, to sales and to revenue – which all add up to a serious commercial inconvenience. What ARE your options here? Risk a design change because there is a high confidence that the fix is understood? Do you roll the dice (the expensive and time consuming ones) and trust that the fix will work? Or spend a week trying to get a few chips fixed using FIB nano-surgery and give yourself some... read more
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