News & Articles

Keep up to date with all the latest NanoScope news and technical articles.

What’s your Sectional Preference?

Combining multiple sectioning methods with other techniques such as laser-assisted-wet-chemical-decapsulation and delayering techniques, can enable access to features buried deep within a complex chiplet or MCM packages.

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IC Designers – Are you missing a trick?

A recent statistic from a well known design tool vendor showed that only 14% of new IC layouts were error free at 1st tape out. Hardly “right first time”.
Verification and modelling will only take you so far, especially for ASIC and Analog designs. High metal layer count, shrinking geometries, packaging developments and thermal issues aren’t helping either.

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🚨 We’re exhibiting at Microelectronics UK 2025 this September!

🚨 We’re exhibiting at Microelectronics UK 2025 this September!

I hope to see you there- DM me now to book a 1 to 1 chat.

Lets talk about…
– FIB IC Nano-surgery for Chip designers to test and de-risk layout changes.
– Failure Analysis for Silicon, III/V’s, PCB’s and Modules, from boards to gates.
– Environmental/Reliability testing – with CSAM and FA support

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Merry 3D X-ray X-mas from NanoScope Services

This X-ray map is of a 3 layer, FIB milled pattern in a 3 layer metal stack (Au, W and Al).
Our Xmas holiday is from 20th Dec to 6th Jan.
As 2024 draws to a close, we wish you a very Merry Christmas and a relaxing break.
For 2025 we hope that your Nano-structures are well formed, your FAB processes well qualified, that your designs are ‘right-first-time’ and failure-free, your packaging and PCBs are reliable and your joints well soldered

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