A recent statistic from a well known design tool vendor showed that only 14% of new IC layouts were error free at 1st tape out. Hardly “right first time”. Verification and modelling will only take you so far, especially for ASIC and Analog designs. High metal layer count, shrinking geometries, packaging developments and thermal issues aren’t helping either. BUT there is a tried and tested way of fixing 1st Silicon in just a few hours. It’s called FIB IC Nano-Surgery (historically called FIB Circuit Edit). For those unfamiliar with the technique, it uses a Focused Ion Beam microscope to physically cut and connect buried tracks on a fabricated IC, correcting layout errors in hours, and allowing you to test and verify a mask change BEFORE tape out. From a business perspective this effectively removes all the risk from such an expensive and time costly decision (new Silicon can take 3 months or more) at a time when a project delivery is at it’s most critical. Who wouldn’t choose to have working Silicon immediately for customer demos, chip, board and system level debug, and project support and investor confidence? HERES the danger – it used to be easy, but now it’s not. A decade ago anyone with a FIB or DualBeam in their lab could implement fixes with a high degree of confidence – but those days are long gone. Devices and packaging got more complex, and the FIB instruments themselves have evolved away from being optimised for Nano-Surgery as an application. So FIB Nano-Surgery has had to evolve, and the people doing it have had to become more specialised....
This has become a routine tool for IC Failure Analysis of Silicon and III/V devices, for FIB IC Nano-Surgery (FIB EDIT), and for Reverse Engineering for IP/Fake/Benchmarking checks. Copper bondwires, III/V die and shrinking package sizes have made it increasingly difficult to use an Acid-only approach to exposing part or all of a die surface. But you can’t just ablate all the plastic and expect the chip to still work, most laser wavelengths damage gates so it is still necessary to use wet chemistry under specific conditions for exposing the die surface....
IC Designers, Failure Analysts and Quality Assurance engineers have a common problem. They need to get into a fabricated IC while keeping it viable and testable. Applications like FIB Nano-surgery, fault localisation by Thermal/Emission imaging or electrical micro-probing, all need the device to function after the Silicon is exposed. This means Decapsulation using Acid is more important than ever, but it’s becoming increasingly difficult with shrinking package sizes and Copper bondwires. Old school Jetetch machines just haven’t kept up. Each lab that offers this has its own unique and hard-won recipes. Ours uses different mixtures of fuming acids, digesters and solvents to clear and clean the die surface without compromising the die attach, bonding, bumps or lead frame. We also vary the temperature to preserve delicate structures and apply Ultrasound too. This all happens AFTER the pre-cavity laser step detailed in my previous post on this topic. This short clip shows the wet chemistry and ultrasonic steps needed to open the full surface of a die (confidential-pixelated), but even this is not the full story. How are you going to test it? Or power it up for imaging the failure mode? Soldering an open device to a test board carries risks from solder and flux damage, and the high temperatures also damage FIB modified devices with a low quality metal deposition (Pt). The simple answer is to use a socket, but can you still image the die surface once it is closed? And if you have remove the top of the package, will it still fit and make good contact? Partial decaps, or chip-and-wire type PCB mounting are straight...
I hope to see you there- DM me now to book a 1 to 1 chat. Lets talk about… – FIB IC Nano-surgery for Chip designers to test and de-risk layout changes. – Failure Analysis for Silicon, III/V’s, PCB’s and Modules, from boards to gates. – Environmental/Reliability testing – with CSAM and FA support. – FAB process qualifications – with nextday referenced metrology data. 📆 24 – 25 Sept | Excel London 🎯 www.microelectronicsuk.com 📍 Booth: H60 hashtag#MicroelectronicsUK hashtag#DeepTech hashtag#SemiconductorDesign Go to LinkedIn...
European / Middle East Issue: Winter 2022 A new IC design FIB Nano-surgery datapoint, our JEDEC MSL Rel-test services and Euros discount. Dear NanoScope Customer, greetings in our first email since COVID. For Silicon DESIGNERS we’ve got a new node success data point, for RELIABILITY Engineers there are new MSL testing services, for EU customers there is our 1€ = 1£ deal, plus NanoScope is growing. First FIB circuit nano-surgery fix to a 7nm node, from the FRONTSIDE. Our unique expertise has allowed us to successfully modify this advanced 7nm process with 13 metal layers at the M2 level, from the front. The device die was then flipchip packaged and tested with a 65% yield. The benefit for the customer concerned was ‘invaluable’. Watch out for the upcoming article on this story. Don’t forget to read our 1st article on ‘How to get the most benefit from IC Nano-Surgery” – part 2 coming soon. Launching our low cost MSL testing service for packaged parts for both R&D and production Reliability. All MSL testing is done to JEDEC standards, but now for the first time customers can choose to have a JEDEC CERTIFIED or an UNCERTIFIED test. R&D lots don’t require certification, so why not save 30% on your MSL trials of new packages? Loading a test lot for Temperature Humidity Bias testing (THB) New colleague – supporting accounts, logistics, orders, quality and billing We’re pleased to introduce Janine Stone, who is now managing project administration and compliance at NanoScope, adding much needed bandwidth for our technical offerings. Contact Janine here. Please welcome Janine Stone to the NanoScope team. We’re re-introducing our 1€ = 1£ exchange rate. To help our EU customers during this period of economic chaos, our 1:1 exchange rate adds clarity, security and a 16%...
There are many advantages of correcting an IC design with FIB Nano-Surgery, but sometimes there are also problems, and many designers have been put off the technique. Did your last FIB work as you expected? Or was the yield low? or you got results you couldn’t explain? A quick recap of the reasons to do a FIB edit and how you would go about it, might be helpful. SCENE: So you’ve taped out your big new design, and 4 months and ₤400,000 /$/€ later, your 1st Silicon devices have arrived for tests to start. And immediately, there’s a problem. If you are lucky, then a normal functional test has failed and after a few days of head scratching it becomes clear what the cause is, and what the most likely metal fix should be. If you are unlucky and it’s more subtle, but still a show stopper for customer acceptance, then the fix strategy may be less obvious. Either way, prompt action is required and there are some difficult decisions to make. Your colleagues, customers and suppliers are all waiting to help get your product to market. Then there is the expense and the delays: to testing, to qualification, to sales and to revenue – which all add up to a serious commercial inconvenience. What ARE your options here? Risk a design change because there is a high confidence that the fix is understood? Do you roll the dice (the expensive and time consuming ones) and trust that the fix will work? Or spend a week trying to get a few chips fixed using FIB nano-surgery and give yourself some...
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